The present invention relates to a switching matrix and more particularly to a broadband digital switching matrix liable to operate at very high frequencies, higher than 100 megabits per second, usable for example for switching digital TV channels.
A switching matrix is a circuit having n input channels and m output channels and permitting to independently apply on any of the m output channels any of the n input channels (or its complement). Each input channel can be connected to a chosen number of outputs. However, an output channel can only be connected to one input channel.
For realizing such a switching matrix, one tries to reach the following objectives:
high operation frequency or low propagation time according to the application (asynchronous or synchronous system), PA1 low current consumption, PA1 low crosstalk ratio, PA1 small size of the circuit when integrated in a silicon wafer. PA1 each input line conductor is connected to an input of a first differential amplifier, each leg of which is associated through a current mirror circuit to a first current source enabled by a selection input of the crosspoint, PA1 the outputs of the differential amplifier are connected to a second differential amplifier fed by a second current source common to all crosspoints of a same column, and PA1 the outputs of the differential pair are connected to the pair of conductors of an output column, an extremity of this column being connected to the high voltage source through a resistor.
In the prior art, to obtain the above mentioned very high operation frequencies, a bipolar technology, for example of the ECL type, which permits reaching such frequencies, is first envisaged. However, with such a technology, the circuit surface is unavoidably important as well as its current consumption.
Thus, one has devised various means for realizing such circuits by using a CMOS technology, that is, a technology comprising N-channel and P-channel MOS transistors: indeed, one knows a priori that such a technology is liable to reduce current consumption and the surface of the circuit. However, the present crosspoint realizations using CMOS transistors exhibit, on the one hand, the drawback of a lack of rapidity, and, on the other hand, the drawback of being incompatible as regards their control voltage with the adjacent circuits for processing high frequency signals, which generally use ECL technology.
For controlling MOS transistors, it is generally necessary that the difference between thigh level and low level is several volts while control levels in ECL technology vary only a few hundred millivolts. Thus, to solve this compatibility problem, it has been necessary to provide circuits for converting the ECL control levels into CMOS control levels and CMOS control levels into ECL control levels. The ECL circuits exhibit the drawback, on the one hand, of requiring a large surface and therefore cancelling part of the advantages expected from CMOS technology and, on the other hand, of adding an important propagation time to the signals, which is particularly impairing when using signal transmission in the synchronous mode.
Moreover, using logic levels having a large difference for controlling MOS transistors causes switching times to be unavoidably long since it is necessary to charge the input capacitors of those MOS transistors and the charging time (dt) is directly proportional to the voltage difference (dV) between high and low levels (dT= CdV/i) for capacitive charges constituted by the gates of the MOS transistors.
An exemplar embodiment of an MOS transistor crosspoint is given in the article by Hyun J. Shin and David A. Hodges issued in IEEE Journal of Solid State Circuits, vol. 24, No. 2, Apr. 1988, entitled "A 250-Mbit/s CMOS Crosspoint Switch". In this article, a few problems associated with the use of MOS transistors are solved as regards the output dispersion of the control signals. By using a specific output amplifier represented in FIG. 7, page 482, of this article, the output voltage dispersion is limited and is compatible with ECL technology. However, the problem concerning the input control of ht MOS transistors is not solved and, as shown in FIG. 8 of this article, one uses for each matrix line an input buffer permitting conversion of ECL logic signals into CMOS logic signals.
An object of the invention is to provide for a switching matrix crosspoint permitting complete insertion of the above problems of ECL/CMOS compatibility and of operation rate.